1. Field of the Invention
This invention relates to a memory device in which non-volatile semiconductor memory cells ar arranged, and more particularly to a memory device in which electrically erasable non-volatile semiconductor memory cells are arranged.
2. Description of the Related Art
The programming operation in the electrically erasable programmable ROM (EEPROM) is effected in substantially the same manner as in the erasable programmable ROM (EPROM) That is, in the programming mode, high voltages are applied to the control gate and the drain of the floating gate type MOSFET to form a strong electric field, causing hot electrons to be generated in the substrate near the drain region. The electrons are injected into the floating gate via the insulating film to change the threshold voltage. In this way, data is programmed into the floating gate type MOSFET. In the erasing mode, a high voltage of 30 V, for example, is applied to the erasing gate of the floating gate type MOSFET to emit the electrons which have been injected into the floating gate, and thus data can be erased.
FIG. 1A is a plan view of a memory cell of the EEPROM having the triple gate structure, and FIG. 1B is a sectional view taken along the I--I line of FIG. 1A. In FIGS. 1A and 1B, CG denotes a control gate, FG a floating gate, EG an erasing gate, S a source and D a drain. The MOS transistor having the triple gate structure is indicated by a symbol shown in FIG. 2A, and the MOS transistor can be represented by an equivalent circuit using coupling capacitors as shown in FIG. 2B. As shown in FIG. 2B, capacitor Ccf is connected between control gate CG and floating gate FG, capacitor Csub is connected between floating gate FG and substrate Sub, capacitor Cdf is connected between drain D and floating gate FG, and capacitor Cef is connected between erasing gate EG and floating gate FG. Assume that charge Qi is injected into floating gate FG in the initial condition of the MOS transistor. Then, charge Qi can be expressed by the following equation: ##EQU1## where Vcg, Vfg, Veg, Vsub and Vd respectively indicate voltages applied to control gate CG, floating aate FG, erasing gate EG, substrate Sub and drain D.
Assume that Ccf+Csub+Cef+Cdf =Ct. Then, voltage Vfg of floating gate FG can be expressed as follows: ##EQU2##
Since, in general, Vsub=0 V and Cef, Cdf &lt;&lt;Ccf equation (1) can be re-written as follows: ##EQU3## where Vfgi=Qi/Ct.
FIG. 3A is a characteristic diagram showing the relation between variation .DELTA.Vth in the threshold voltage and programming time Tpw required for programming data into the MOS transistor having the triple gate structure shown in FIG. 2A with control gate voltage Vcg used as a parameter and with drain voltage Vd kept at a constant value. In FIG. 3A, broken line I indicates a characteristic obtained in a case where control gate voltage Vcg is set to be relatively high and solid line II indicates a characteristic obtained in a case where control gate voltage Vcg is set to be relatively low. FIG. 3B is a characteristic diagram showing the relation between control voltage Vcg and variation .DELTA.Vth in the threshold voltage in a case where data is programmed into the MOS transistor with drain voltage Vd and programming time Tpw kept constant.
In general, the operation of programming data into the EPROM having a memory cell formed of a MOS transistor with the double gate structure is different from the operation of programming data into the EEPROM having a memory cell formed of a MOS transistor with the triple gate structure in the following point. That is, in the former data programming operation, the larger amount of electrons can be injected into floating gate FG to attain a better programming characteristic as control gate voltage Vcg applied to control gate CG is set to a higher voltage level as is disclosed in U.S. Pat. No. 4,597,062. In contrast, as shown in FIGS. 3A and 3B, in the latter data programming operation, variation .DELTA.Vth in tee threshold voltage becomes small when control gate voltage Vcg exceeds a certain voltage level, lowering the programming characteristic.
The above program may occur based on the following fact. In the EEPROM cell, floating gate FG will be positively charged after the electrons trapped in floating gate FG are removed and data is erased. In the programming mode in which data is programmed again, the potential of floating gate FG becomes too high to form an inversion layer in the substrate directly under floating gate FG when voltage Vcg applied to control gate CG exceeds a certain voltage level. As a result, it becomes difficult to concentrate the electric field in the pinch-off region in the substrate near drain D. For example, unlike the EEPROM, in the EPROM, floating gate voltage Vfg is set to be approx. 12 V based on equation (2) if Cef/Ct=0.57 and when drain voltage Vd=15 V is applied to drain D and control gate voltage Vcg=21 V is applied to the control gate with floating gate voltage Vfgi kept at 0 V. As a result, the cell transistor is operated in the pentode operation mode and sufficiently large amount of hot electrons are generated in the pinch-off region of the substrate near the drain, causing the electrons to be efficiently injected into the floating gate. In contrast, in the EEPROM, the floating gate will be positively charged in a condition in which data is fully erased. For example, the floating gate is positively charged so that potential Vfgi may be set to +6 V. Even if drain voltage Vd=15 V is applied to the drain and control gate voltage Vcg=21 V is applied to the control gate in the same manner as in the case of the EPROM, the floating gate voltage will become as high as 18 V. If data is programmed into the memory cell in this condition, an inversion layer is formed in the substrate directly under the floating gate and the memory cell transistor will be operated in the triode operation mode. As a result, no pinch-off region is created in the memory cell transistor and a sufficiently large amount of hot electrons cannot be generated in the substrate, thus lowering the efficiency of injecting the hot electrons into the floating gate.